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tps54341 www.ti.com slvsc61 ? november 2013 4.5-v to 42-v input, 3.5-a step-down dc-dc converter with soft-start and eco-mode ? check for samples: tps54341 1 features description the tps54341 device is a 42-v 3.5-a step-down 23 ? high efficiency at light loads with pulse regulator with an integrated high-side mosfet. the skipping eco-mode ? device survives load-dump pulses up to 45 v per iso ? 87-m high-side mosfet 7637. current mode control provides simple external ? 152- a operating quiescent current and compensation and flexible component selection. a low-ripple pulse-skip mode reduces the no-load 2- a shutdown current supply current to 152 a. shutdown supply current is ? 100-khz to 2.5-mhz adjustable switching reduced to 2 a when the enable pin is pulled low. frequency undervoltage lockout is internally set at 4.3 v but can ? synchronizes to external clock increase using an external resistor divider at the ? low dropout at light loads with integrated enable pin. the output voltage startup ramp is boot recharge fet controlled by the soft start pin that can also be ? adjustable uvlo voltage and hysteresis configured for sequencing/tracking. an open-drain power-good signal indicates the output is within 93% ? uv and ov power-good output to 106% of the nominal voltage. ? adjustable soft-start and sequencing a wide adjustable switching-frequency range allows ? 0.8-v 1% internal voltage reference for optimization of either efficiency or external ? 10-pin son with thermal pad package component size. cycle-by-cycle current limit, ? ? 40 c to 150 c t j operating range frequency foldback and thermal shutdown protects internal and external components during an overload ? supported by webench ? software tool condition. applications the tps54341 device is available in a 10-pin 4-mm 4-mm son package. ? industrial automation and motor control ? vehicle accessories: gps (see slva412 ), entertainment ? usb-dedicated charging ports and battery chargers (see slva464 ) ? 12-v and 24-v industrial, automotive and communications power systems simplified schematic efficiency vs load current 1 please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 2 eco-mode is a trademark of texas instruments. 3 webench is a registered trademark of texas instruments. production data information is current as of publication date. copyright ? 2013, texas instruments incorporated products conform to specifications per the terms of the texas instruments standard warranty. production processing does not necessarily include testing of all parameters. 60 65 70 75 80 85 90 95 100 0 0.5 1 1.5 2 2.5 3 3.5 efficiency (%) i o - output current (a) c099 v out = 12 v, f sw = 620 khz, v out = 5 v and 3.3 v, f sw = 400 khz 12 v to 5 v 12 v to 3.3 v 36 v to 12 v sw vin gnd boot fb comp en rt/clk v in v out tps54341 ss/tr pwrgd
tps54341 slvsc61 ? november 2013 www.ti.com this integrated circuit can be damaged by esd. texas instruments recommends that all integrated circuits be handled with appropriate precautions. failure to observe proper handling and installation procedures can cause damage. esd damage can range from subtle performance degradation to complete device failure. precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. device information pin configuration dpr package (top view) pin functions pin i/o description name no. a bootstrap capacitor is required between boot and sw. if the voltage on this capacitor is below the boot 1 o minimum required to operate the high-side mosfet, the gate drive switches off until the capacitor refreshes. error amplifier output and input to the output switch current (pwm) comparator. connect frequency comp 7 o compensation components to this pin. enable pin, with internal pullup current source. pull below 1.2 v to disable. float to enable. adjust the input en 3 i undervoltage lockout with two resistors. see the enable and adjusting undervoltage lockout section. fb 6 i inverting input of the transconductance (gm) error amplifier. gnd 8 ? ground power good is an open drain output that asserts low if the output voltage is out of regulation due to thermal pwrgd 10 o shutdown, dropout, over-voltage or en shut down resistor timing and external clock. an internal amplifier holds this pin at a fixed voltage when using an external resistor to ground to set the switching frequency. if the pin is pulled above the pll upper threshold, rt/clk 5 i a mode change occurs and the pin becomes a synchronization input. the internal amplifier is disabled and the pin is a high-impedance clock input to the internal pll. if clocking edges stop, the internal amplifier re- enables and the operating mode returns to resistor frequency programming. soft-start and tracking. an external capacitor connected to this pin sets the output rise time. because the ss/tr 4 i voltage on this pin overrides the internal reference, ss/tr can be used for tracking and sequencing. sw 9 i the source of the internal high-side power mosfet and switching node of the converter. vin 2 i input supply voltage with 4.5-v to 42-v operating range. the gnd pin must be electrically connected to the exposed pad on the printed circuit board for proper thermal pad 11 ? operation. 2 submit documentation feedback copyright ? 2013, texas instruments incorporated product folder links: tps54341 boot vin en ss/tr rt/clk pwrgdsw gnd comp fb 10 9 1 2 3 4 5 87 6
tps54341 www.ti.com slvsc61 ? november 2013 functional block diagram copyright ? 2013, texas instruments incorporated submit documentation feedback 3 product folder links: tps54341 error amplifier boot charge boot uvlo uvlo current sense oscillator with pll frequency foldback logic slope compensation pwm comparator minimum clamp pulse skip maximum clamp voltage reference overload recovery fb comp rt/ clk sw boot vin gnd thermal shutdown en enable comparator shutdown logic shutdown enable threshold 6 10/9/2013 a0272435 logic shutdown powerpad shutdown uv ss/tr pwrgd ov
tps54341 slvsc61 ? november 2013 www.ti.com absolute maximum ratings (1) over operating free-air temperature range (unless otherwise noted) value unit min max vin ? 0.3 45 en ? 0.3 8.4 boot 53 fb ? 0.3 3 input voltage v comp ? 0.3 3 pwrgd ? 0.3 6 ss/tr ? 0.3 3 rt/clk ? 0.3 3.6 boot-sw 8 output voltage sw ? 0.6 45 v sw, 10-ns transient ? 2 45 electrostatic discharge (hbm) qss 009-105 (jesd22-a114a) 2 kv electrostatic discharge (cdm) qss 009-147 (jesd22-c101b.01) 500 v operating junction temperature ? 40 150 c storage temperature ? 65 150 c (1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. thermal information tps54341 thermal metric (1) (2) units dpr (10 pins) ja junction-to-ambient thermal resistance (standard board) 35.1 jt junction-to-top characterization parameter 0.3 jb junction-to-board characterization parameter 12.5 c/w jctop junction-to-case(top) thermal resistance 34.1 jcbot junction-to-case(bottom) thermal resistance 2.2 jb junction-to-board thermal resistance 12.3 (1) for more information about traditional and new thermal metrics, see the ic package thermal metrics application report, spra953 . (2) power rating at a specific ambient temperature ta should be determined with a junction temperature of 150 c. this is the point where distortion starts to substantially increase. see power dissipation estimate in application section of this data sheet for more information. 4 submit documentation feedback copyright ? 2013, texas instruments incorporated product folder links: tps54341
tps54341 www.ti.com slvsc61 ? november 2013 electrical characteristics t j = ? 40 c to 150 c, vin = 4.5 to 42 v (unless otherwise noted) parameter test conditions min typ max unit supply voltage (vin pin) operating input voltage 4.5 42 v internal undervoltage lockout rising 4.1 4.3 4.48 v threshold internal undervoltage lockout 325 mv threshold hysteresis shutdown supply current en = 0 v, 25 c, 4.5 v vin 42 v 2.25 4.5 a operating: nonswitching supply fb = 0.9 v, t a = 25 c 152 200 current enable and uvlo (en pin) enable threshold voltage no voltage hysteresis, rising and falling 1.1 1.2 1.3 v enable threshold +50 mv ? 4.6 input current a enable threshold ? 50 mv ? 0.58 ? 1.2 ? 1.8 hysteresis current ? 2.2 ? 3.4 ? 4.5 a enable to comp active v in = 12 v, t a = 25 c 540 s voltage reference voltage reference 0.792 0.8 0.808 v high-side mosfet on-resistance vin = 12 v, boot-sw = 6 v 87 185 m error amplifier input current 50 na error amplifier transconductance ? 2 a < i comp < 2 a, v comp = 1 v 350 mhos (gm) error amplifier transconductance ? 2 a < i comp < 2 a, v comp = 1 v, v fb = 0.4 v 77 mhos (gm) during soft-start error amplifier dc gain v fb = 0.8 v 10 000 v/v min unity gain bandwidth 2500 khz error amplifier source and sink v (comp) = 1 v, 100-mv overdrive 30 a comp to sw current 12 a/v transconductance current limit all vin and temperatures, open loop (1) 4.5 5.5 6.8 current limit threshold all temperatures, vin = 12 v, open loop (1) 4.5 5.5 6.3 a vin = 12 v, t a = 25 c, open loop (1) 5.2 5.5 5.9 current limit threshold delay 60 ns thermal shutdown thermal shutdown 176 c thermal shutdown hysteresis 12 c timing resistor and external clock (rt/clk pin) switching frequency range using rt 100 2500 khz mode ? sw switching frequency r t = 200 k 450 500 550 khz switching frequency range using clk 160 2300 khz mode minimum clk input pulse width 15 ns rt/clk high threshold 1.55 2 v rt/clk low threshold 0.5 1.2 v rt/clk falling edge to sw rising measured at 500 khz with rt resistor in series 55 ns edge delay pll lock in time measured at 500 khz 78 s soft start and tracking (ss/tr pin) charge current v ss/tr = 0.4 v 1.7 a (1) open loop current limit measured directly at the sw pin and is independent of the inductor value and slope compensation. copyright ? 2013, texas instruments incorporated submit documentation feedback 5 product folder links: tps54341
tps54341 slvsc61 ? november 2013 www.ti.com electrical characteristics (continued) t j = ? 40 c to 150 c, vin = 4.5 to 42 v (unless otherwise noted) parameter test conditions min typ max unit ss/tr-to-fb matching v ss/tr = 0.4 v 42 mv ss/tr-to-reference crossover 98% nominal 1.16 v ss/tr discharge current (overload) fb = 0 v, v ss/tr = 0.4 v 354 a ss/tr discharge voltage fb = 0 v 54 mv power good (pwrgd pin) fb threshold for pwrgd low fb falling 90 % fb threshold for pwrgd high fb rising 93 % fb threshold for pwrgd low fb rising 108 % fb threshold for pwrgd high fb falling 106 % hysteresis fb falling 2.5 % output high leakage v pwrgd = 5.5 v, t a = 25 c 10 na on resistance i pwrgd = 3 ma, v fb < 0.79 v 45 minimum vin for defined output v pwrgd < 0.5 v, i pwrgd = 100 a 0.9 2 v 6 submit documentation feedback copyright ? 2013, texas instruments incorporated product folder links: tps54341
tps54341 www.ti.com slvsc61 ? november 2013 typical characteristics on resistance voltage reference vs vs junction temperature junction temperature figure 1. figure 2. switch current limit switch current limit vs vs junction temperature input voltage figure 3. figure 4. switching frequency switching frequency vs vs rt/clk resistance junction temperature low frequency range figure 5. figure 6. copyright ? 2013, texas instruments incorporated submit documentation feedback 7 product folder links: tps54341 450 460 470 480 490 500 510 520 530 540 550 50 25 0 25 50 75 100 125 150 f s - switching frequency (khz) t j junction - temperature ( ? c) rt = 200 kohm, vin = 12 v c005 rt = 200 k , v in = 12 v 100 150 200 250 300 350 400 450 500 200 300 400 500 600 700 800 900 1,000 f sw - switching frequency (khz) rt/clk - resistance (k ) c006 0 10 20 30 40 50 60 70 80 90 100 0.001 0.01 0.1 1 efficiency (%) output current (a) vin = 7v vin = 12v vin = 24v vin = 36v c004 v in = 7 v v in = 12 v v in = 24 v v in = 36 v v out 9| sw = 600 khz 4.5 4.7 4.9 5.1 5.3 5.5 5.7 5.9 6.1 6.3 6.5 50 25 0 25 50 75 100 125 150 high slide switch current (a) t j junction - temperature ( ? c) vin = 12 v c003 v in = 12 v 0 0.05 0.1 0.15 0.2 0.25 50 25 0 25 50 75 100 125 150 rdson - static drain-source on-state resistance ( ) t j junction - temperature ( ? c) boot-sw = 3 v boot-sw = 6 v c001 0.784 0.789 0.794 0.799 0.804 0.809 0.814 50 25 0 25 50 75 100 125 150 v fb - voltage reference (v) t j junction - temperature ( ? c) vin = 12 v c002 v in = 12 v
tps54341 slvsc61 ? november 2013 www.ti.com typical characteristics (continued) switching frequency vs ea transconductance rt/clk resistance vs high frequency range junction temperature figure 7. figure 8. ea transconductance during soft-start en pin voltage vs vs junction temperature junction temperature figure 9. figure 10. en pin current en pin current vs vs junction temperature junction temperature figure 11. figure 12. 8 submit documentation feedback copyright ? 2013, texas instruments incorporated product folder links: tps54341 5.5 5.3 5.1 4.9 4.7 4.5 4.3 4.1 3.9 3.7 3.5 50 25 0 25 50 75 100 125 150 current i en (ua) t j junction - temperature ( ? c) vin = 12 v, ien = threshold + 50 mv c011 v in = 12 v, i en = threshold + 50 mv 2.5 2.3 2.1 1.9 1.7 1.5 1.3 1.1 0.9 0.7 0.5 50 25 0 25 50 75 100 125 150 current i en (ua) t j junction - temperature ( ? c) vin = 12 v, ien = threshold + 50 mv c012 v in = 12 v, i en = threshold - 50 mv 20 30 40 50 60 70 80 90 100 110 120 50 25 0 25 50 75 100 125 150 gm - ua/v t j junction - temperature ( ? c) vin = 12 v c009 v in = 12 v 1.15 1.18 1.21 1.24 1.27 1.3 50 25 0 25 50 75 100 125 150 en - threshold (v) t j junction - temperature ( ? c) vin = 12 v c010 v in = 12 v 200 250 300 350 400 450 500 50 25 0 25 50 75 100 125 150 gm - ua/v t j junction - temperature ( ? c) vin = 12 v c008 v in = 12 v 0 500 1,000 1,500 2,000 2,500 0 50 100 150 200 f sw - switching frequency (khz) rt/clk - resistance (k ) c007
tps54341 www.ti.com slvsc61 ? november 2013 typical characteristics (continued) en pin current hysteresis switching frequency vs vs junction temperature fb figure 13. figure 14. shutdown supply current shutdown supply current vs vs junction temperature input voltage (v in ) figure 15. figure 16. v in supply current v in supply current vs vs junction temperature input voltage figure 17. figure 18. copyright ? 2013, texas instruments incorporated submit documentation feedback 9 product folder links: tps54341 70 90 110 130 150 170 190 210 50 25 0 25 50 75 100 125 150 supply current i vin (ua) t j junction - temperature ( ? c) vin = 12 v c017 v in = 12 v 70 90 110 130 150 170 190 210 0 5 10 15 20 25 30 35 40 45 supply current i vin (ua) v in - input voltage ( ? c) vin = 12 v c018 t j = 25 c 0 0.5 1 1.5 2 2.5 3 50 25 0 25 50 75 100 125 150 supply current i vin (ua) t j junction - temperature ( ? c) vin = 12 v c015 v in = 12 v 0 0.5 1 1.5 2 2.5 3 0 5 10 15 20 25 30 35 40 45 supply current i vin (ua) v in - input voltage ( ? c) vin = 12 v c016 t j = 25 c 4.5 4.3 4.1 3.9 3.7 3.5 3.3 3.1 2.9 2.7 2.5 50 25 0 25 50 75 100 125 150 i en hysteresis (ua) t j junction - temperature ( ? c) vin = 12 v c013 v in = 12 v 0.0 25.0 50.0 75.0 100.0 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 nominal switching frequency (%) v sense (v) vsense falling vsense falling c014 v sense falling v sense rising
tps54341 slvsc61 ? november 2013 www.ti.com typical characteristics (continued) boot-sw uvlo input voltage uvlo vs vs junction temperature junction temperature figure 19. figure 20. pwrgd on resistance pwrgd threshold vs vs junction temperature junction temperature figure 21. figure 22. ss/tr to fb offset ss/tr to fb offset vs vs fb temperature figure 23. figure 24. 10 submit documentation feedback copyright ? 2013, texas instruments incorporated product folder links: tps54341 20 25 30 35 40 45 50 55 60 50 25 0 25 50 75 100 125 150 ss/tr to fb offset (mv) t j junction - temperature ( ? c) vin = 12 v, fb = 0.4 v c025 v in = 12 v, fb = 0.4 v 0 100 200 300 400 500 600 700 800 900 0 100 200 300 400 500 600 700 800 offset (mv) ss/tr (mv) vin = 12 v, 25 c c024 v in = 12 v, 25 c 0 10 20 30 40 50 60 70 80 50 25 0 25 50 75 100 125 150 power good resistance ( ) t j junction - temperature ( ? c) vin = 12 v c021 v in = 12 v 88 90 92 94 96 98 100 102 104 106 108 110 50 25 0 25 50 75 100 125 150 power good threshold (%) t j junction - temperature ( ? c) c022 v in = 12 v fb rising fb rising fb falling fb falling 1.8 1.9 2 2.1 2.2 2.3 2.4 2.5 2.6 50 25 0 25 50 75 100 125 150 vi(boot-ph) (v) t j junction - temperature ( ? c) boot-ph uvlo falling boot-ph uvlo rising c019 3.7 3.8 3.9 4 4.1 4.2 4.3 4.4 4.5 50 25 0 25 50 75 100 125 150 v in (v) t j junction - temperature ( ? c) uvlo start switching uvlo stop switching c020
tps54341 www.ti.com slvsc61 ? november 2013 typical characteristics (continued) 5-v start and stop voltage (see low dropout operation and bootstrap voltage (boot) ) figure 25. copyright ? 2013, texas instruments incorporated submit documentation feedback 11 product folder links: tps54341 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5 5.6 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 v in (v) output current (a) start stop c026 dropout voltage dropout voltage
tps54341 slvsc61 ? november 2013 www.ti.com overview the tps54341 device is a 42-v 3.5-a, step-down (buck) regulator with an integrated high-side n-channel mosfet. the device implements constant-frequency current-mode control which reduces output capacitance and simplifies external frequency compensation. the wide switching frequency range of 100 to 2500 khz allows for either efficiency or size optimization when selecting the output filter components. the switching frequency is adjusted using a resistor to ground connected to the rt/clk pin. the device has an internal phase-locked loop (pll) connected to the rt/clk pin that synchronizes the power switch turn-on to a falling edge of an external clock signal. the tps54341 device has a default input-startup voltage of 4.3 v typical. the en pin adjusts the input-voltage undervoltage-lockout (uvlo) threshold with two external resistors. an internal-pullup current source enables operation when the en pin is floating. the operating current is 152 a under a no-load condition when not switching. when the device is disabled, the supply current is 2 a. the integrated 87-m high-side mosfet supports high-efficiency power-supply designs capable of delivering 3.5 a of continuous current to a load. the gate-drive bias voltage for the integrated high-side mosfet is supplied by a bootstrap capacitor connected from the boot to sw pins. the tps54341 device reduces the external component count by integrating the bootstrap recharge diode. the boot pin capacitor voltage is monitored by a uvlo circuit which turns off the high-side mosfet when the boot to sw voltage falls below a preset threshold. an automatic boot capacitor recharge circuit allows the tps54341 device to operate at high duty cycles approaching 100%. therefore, the maximum output voltage is near the minimum input supply voltage of the application. the minimum output voltage is the internal 0.8-v feedback reference. output overvoltage transients are minimized by an overvoltage protection (ovp) comparator. when the ovp comparator is activated, the high-side mosfet turns off and remains off until the output voltage is less than 106% of the desired output voltage. the ss/tr (soft-start/tracking) pin minimizes inrush currents or provides power-supply sequencing during power up. a small value capacitor must be connected to the pin to adjust the soft-start time. a resistor divider can be connected to the pin for critical power-supply sequencing requirements. the ss/tr pin is discharged before the output powers up. this discharging ensures a repeatable restart after an overtemperature fault, uvlo fault, or a disabled condition. when the overload condition is removed, the soft-start circuit controls the recovery from the fault output level to the nominal regulation voltage. a frequency-foldback circuit reduces the switching frequency during startup and overcurrent fault conditions to help maintain control of the inductor current. detailed description fixed frequency pwm control the tps54341 device uses fixed-frequency peak-current-mode control with adjustable switching frequency. the output voltage is compared through external resistors connected to the fb pin to an internal voltage reference by an error amplifier. an internal oscillator initiates the turn-on of the high-side power switch. the error amplifier output at the comp pin controls the high-side power switch current. when the high-side mosfet switch current reaches the threshold level set by the comp voltage, the power switch turns off. the comp pin voltage increases and decreases as the output current increases and decreases. the device implements current limiting by clamping the comp pin voltage to a maximum level. the pulse skipping eco-mode is implemented with a minimum voltage clamp on the comp pin. slope compensation output current the tps54341 device adds a compensating ramp to the mosfet switch current-sense signal. this slope compensation prevents sub-harmonic oscillations at duty cycles greater than 50%. the peak current limit of the high-side switch is not affected by the slope compensation and remains constant over the full duty-cycle range. pulse skip eco-mode the tps54341 device operates in a pulse-skipping eco-mode at light load currents to improve efficiency by reducing switching and gate drive losses. if the output voltage is within regulation and the peak switch current at the end of any switching cycle is below the pulse skipping current threshold, the device enters eco-mode. the pulse-skipping current threshold is the peak switch-current level corresponding to a nominal comp voltage of 600 mv. 12 submit documentation feedback copyright ? 2013, texas instruments incorporated product folder links: tps54341
tps54341 www.ti.com slvsc61 ? november 2013 detailed description (continued) when in eco-mode, the comp pin voltage is clamped at 600 mv and the high-side mosfet is inhibited. because the device is not switching, the output voltage begins to decay. the voltage-control loop responds to the falling output voltage by increasing the comp pin voltage. the high-side mosfet enables and switching resumes when the error amplifier lifts comp above the pulse skipping threshold. the output voltage recovers to the regulated value, and comp eventually falls below the eco-mode pulse skipping threshold at which time the device again enters eco-mode. the internal pll remains operational when in eco-mode. when operating at light load currents in eco-mode, the switching transitions occur synchronously with the external clock signal. during eco-mode operation, the tps54341 device senses and controls peak switch current, not the average load current. therefore the load current at which the device enters eco-mode is dependent on the output inductor value. the circuit in figure 46 enters eco-mode at 30-ma output current. as the load current approaches zero, the device enters a pulse-skip mode during which it draws only 152- a input quiescent current. low dropout operation and bootstrap voltage (boot) the tps54341 device provides an integrated bootstrap-voltage regulator. a small capacitor between the boot and sw pins provides the gate-drive voltage for the high-side mosfet. the boot capacitor refreshes when the high-side mosfet is off and the external low-side diode conducts. the recommended value of the boot capacitor is 0.1 f. a ceramic capacitor with an x7r or x5r grade dielectric with a voltage rating of 10 v or higher is recommended for stable performance over temperature and voltage. when operating with a low voltage difference from input to output, the high-side mosfet of the tps54341 device operates at 100% duty cycle as long as the boot to sw pin voltage is greater than 2.1 v. when the voltage from boot to sw drops below 2.1 v, the high-side mosfet turns off and an integrated low-side mosfet pulls sw low to recharge the boot capacitor. to reduce the losses of the small low-side mosfet at high output voltages, the low-side mosfet is disabled at 24 v output and re-enabled when the output reaches 21.5 v. because the gate-drive current sourced from the boot capacitor is small, the high-side mosfet remains on for many switching cycles before the mosfet turns off to refresh the capacitor. thus the effective duty cycle of the switching regulator can be high, approaching 100%. the effective duty cycle of the converter during dropout is mainly influenced by the voltage drops across the power mosfet, the inductor resistance, the low-side diode voltage, and the printed circuit-board resistance. the start and stop voltage for a typical 5-v output application is shown in figure 25 where the input voltage is plotted versus load current. the start voltage is defined as the input voltage required to regulate the output within 1% of nominal. the stop voltage is defined as the input voltage at which the output drops by 5% or where switching stops. during high duty-cycle (low dropout) conditions, inductor current-ripple increases when the boot capacitor recharges resulting in an increase in output-voltage ripple. increased ripple occurs when the off time required to recharge the boot capacitor is longer than the high-side off time associated with cycle-by-cycle pwm control. at heavy loads, the minimum input voltage must increase to ensure a monotonic startup. equation 1 calculates the minimum input voltage for this condition. (1) where ? d (max) 0.9 ? v d = forward drop of the catch diode ? vboot = (1.41 v in ? 0.554 ? v d ? sw ? 1.847 10 3 ib2sw) / (1.41 + ? sw ) ? r ds(on) = 1 / ( ? 0.3 vb2sw 2 + 3.577 vb2sw ? 4.246) ? ib2sw = 100 a ? vb2sw = vboot + v d copyright ? 2013, texas instruments incorporated submit documentation feedback 13 product folder links: tps54341 out(max) (max) in(min) out(max) ds(on) d d out(max) dc v d x (v - i x r v ) - v i x r = + +
tps54341 slvsc61 ? november 2013 www.ti.com detailed description (continued) error amplifier a transconductance error amplifier controls the tps54341 device voltage-regulation loop. the error amplifier compares the fb pin voltage to the lower of the internal soft-start voltage or the internal 0.8-v voltage reference. the transconductance (gm) of the error amplifier is 350 a/v during normal operation. during soft-start operation, the transconductance is reduced to 78 a/v and the error amplifier is referenced to the internal soft- start voltage. the frequency compensation components (capacitor, series resistor, and capacitor) are connected between the error amplifier output comp pin and gnd pin. adjusting the output voltage the internal voltage reference produces a precise 0.8-v 1% voltage reference over the operating temperature and voltage range by scaling the output of a bandgap-reference circuit. the output voltage is set by a resistor divider from the output node to the fb pin. using 1% tolerance or better divider resistors is recommended. select the low-side resistor r ls for the desired divider current and use equation 2 to calculate r hs . to improve efficiency at light loads consider using larger value resistors. however, if the values are too high, the regulator is more susceptible to noise and voltage errors from the fb input current may become noticeable. (2) enable and adjusting undervoltage lockout the tps54341 device enables when the vin pin voltage rises above 4.3 v and the en pin voltage exceeds the enable threshold of 1.2 v. the tps54341 device disables when the vin pin voltage falls below 4 v or when the en pin voltage is below 1.2 v. the en pin has an internal pullup-current source, i 1 , of 1.2 a that enables operation of the tps54341 device when the en pin floats. if an application requires a higher undervoltage-lockout (uvlo) threshold, use the circuit shown in figure 26 to adjust the input-voltage uvlo with two external resistors. when the en pin voltage exceeds 1.2 v, an additional 3.4 a of hysteresis current, i hys , is sourced out of the en pin. when the en pin pulls below 1.2 v, the 3.4- a i hys current is removed. this additional current facilitates adjustable input-voltage uvlo hysteresis. use equation 3 to calculate r uvlo1 for the desired uvlo hysteresis voltage. use equation 4 to calculate r uvlo2 for the desired vin start voltage. in applications designed to start at relatively low input voltages (that is, from 4.5 o 9 v) and withstand high input voltages (for example, 40 v), the en pin can experience a voltage greater than the absolute maximum voltage of 8.4 v during the high-input voltage condition. to avoid exceeding this voltage when using the en resistors, the en pin is clamped internally with a 5.8-v zener diode capable of sinking up to 150 a. (3) (4) 14 submit documentation feedback copyright ? 2013, texas instruments incorporated product folder links: tps54341 = - + ena uvlo2 start ena 1 uvlo1 v r v v i r - = start stop uvlo1 hys v v r i hs ls vout 0.8v r = r 0.8 v - ? ? ? ?
tps54341 www.ti.com slvsc61 ? november 2013 detailed description (continued) figure 26. adjustable uvlo figure 27. internal en pin clamp soft-start/tracking pin (ss/tr) the tps54341 device effectively uses the lower voltage of the internal voltage reference or the ss/tr pin voltage as the reference voltage of the power-supply and regulates the output accordingly. a capacitor on the ss/tr pin to ground implements a soft-start time. the tps54341 device has an internal pullup-current source of 1.7 a that charges the external soft-start capacitor. the calculations for the soft-start time (10% to 90%) are shown in equation 5 . the voltage reference (v ref ) is 0.8 v and the soft-start current (i ss ) is 1.7 a. the soft-start capacitor should remain lower than 0.47 f and greater than 0.47 nf. (5) at power up, the tps54341 device does not start switching until the soft-start pin discharges to less than 54 mv to ensure a proper power-up, see figure 28 . also, during normal operation, the tps54341 device stops switching and the ss/tr must discharge to 54 mv, when the vin uvlo is exceeded, the en pin pulls below 1.2 v, otherwise a thermal shutdown event occurs. the fb voltage follows the ss/tr pin voltage with a 42-mv offset up to 85% of the internal voltage reference. when the ss/tr voltage is greater than 85% on the internal reference voltage the offset increases as the effective system reference transitions from the ss/tr voltage to the internal voltage reference (see figure 23 ). the ss/tr voltage ramps linearly until clamped at 2.7 v typically as shown in figure 28 . figure 28. operation of ss/tr pin when starting copyright ? 2013, texas instruments incorporated submit documentation feedback 15 product folder links: tps54341 ss ss ss ref t (ms) i (a) c (nf) = v (v) 0.8 tps54341 i vin r uvlo1 r uvlo2 en v en ihys 1 vin r uvlo1 r uvlo2 en node 5.8 v 10 k w tps54341
tps54341 slvsc61 ? november 2013 www.ti.com detailed description (continued) sequencing many of the common power-supply sequencing methods are implemented using the ss/tr, en, and pwrgd pins. the sequential method is implemented using an open-drain output of a power-on reset pin of another device. the sequential method is illustrated in figure 29 using two tps54341 devices. the power good is connected to the en pin on the tps54341 device which enables the second power supply once the primary supply reaches regulation. if needed, a 1-nf ceramic capacitor on the en pin of the second power supply provides a 1-ms startup delay. figure 30 shows the results of figure 29 . figure 29. schematic for sequential startup figure 30. sequential startup using en and sequence pwrgd figure 31. schematic for ratiometric startup figure 32. ratiometric startup using coupled sequence ss/tr pins figure 31 shows a method for ratiometric start-up sequence by connecting the ss/tr pins together. the regulator outputs ramp up and reach regulation at the same time. when calculating the soft-start time the pullup current source must be doubled in equation 5 . figure 32 shows the results of figure 31 . 16 submit documentation feedback copyright ? 2013, texas instruments incorporated product folder links: tps54341 en tps54160 3 ss/tr 4 pwrgd 6 en tps54160 3 ss/tr 4 pwrgd 6 tps54341 tps54341 ss /tr tps54341 en pwrgd ss /tr en pwrgd tps54341
tps54341 www.ti.com slvsc61 ? november 2013 detailed description (continued) figure 33. schematic for ratiometric and simultaneous startup sequence ratiometric and simultaneous power-supply sequencing is implemented by connecting the resistor network of r1 and r2 shown in figure 33 to the output of the power supply that must be tracked or another voltage reference source. using equation 6 and equation 7 , calculate the tracking resistors to initiate the v out2 slightly before, after, or at the same time as v out1 . equation 8 is the voltage difference between v out1 and v out2 at the 95% of nominal output regulation. the v variable is 0 v for simultaneous sequencing. to minimize the effect of the inherent ss/tr to fb offset (v ssoffset ) in the soft-start circuit and the offset created by the pullup-current source (i ss ) and tracking resistors, the v ssoffset and i ss are included as variables in the equations. to design a ratiometric start-up in which the v out2 voltage is slightly greater than the v out1 voltage when v out2 reaches regulation, use a negative number in equation 6 through equation 8 for v. equation 8 results in a positive number for applications which the v out2 is slightly lower than v out1 when v out2 regulation is achieved. because the ss/tr pin must be pulled below 54 mv before starting after an en, uvlo, or thermal shutdown fault, careful selection of the tracking resistors is required to ensure the device restarts after a fault. the calculated r1 value from equation 6 must be greater than the value calculated in equation 9 to ensure the device recovers from a fault. as the ss/tr voltage becomes more than 85% of the nominal reference voltage, the v ssoffset becomes larger as the soft-start circuits gradually hands-off the regulation reference to the internal voltage reference. the ss/tr pin voltage must be greater than 1.5 v for a complete handoff to the internal voltage reference. (6) (7) (8) (9) copyright ? 2013, texas instruments incorporated submit documentation feedback 17 product folder links: tps54341 out1 r1 2800 v 180 v > - d out1 out2 v v v d = - ref out2 ref v r1 r2 v v v = + d - out2 ssoffset ref ss v v v r1 v i + d = ss/tr tps54341 en pwrgd ss/ tr en pwrgd vout 1 vout 2 r 1 r 2 r3 r 4 tps54341
tps54341 slvsc61 ? november 2013 www.ti.com detailed description (continued) figure 34. ratiometric startup with tracking figure 35. ratiometric startup with tracking resistors resistors figure 36. simultaneous startup with tracking resistor constant switching frequency and timing resistor (rt/clk) pin) the switching frequency of the tps54341 device is adjustable over a wide range from 100 to 2500 khz by placing a resistor between the rt/clk pin and gnd pin. the rt/clk pin voltage is typically 0.5 v and must have a resistor to ground to set the switching frequency. to determine the timing resistance for a given switching frequency, use equation 10 or equation 11 or the curves in figure 5 and figure 6 . to reduce the solution size, one typically sets the switching frequency as high as possible. tradeoffs of the conversion efficiency, maximum input voltage, and minimum controllable on time must be considered. the minimum controllable on time is typically 135 ns which limits the maximum operating frequency in applications with high input-to-output step-down ratios. the maximum switching frequency is also limited by the frequency-foldback circuit. a more detailed discussion of the maximum switching frequency is provided in the next section. (10) (11) 18 submit documentation feedback copyright ? 2013, texas instruments incorporated product folder links: tps54341 sw 1.008 101756 ? (khz) rt (k ) = w 0.991 sw 92 417 rt (k ) ? (khz) w =
tps54341 www.ti.com slvsc61 ? november 2013 detailed description (continued) accurate current limit operation and maximum switching frequency the tps54341 device implements peak-current-mode control in which the comp pin voltage controls the peak current of the high-side mosfet. a signal proportional to the high-side switch current and the comp pin voltage are compared each cycle. when the peak switch current intersects the comp control voltage, the high-side switch turns off. during overcurrent conditions that pull the output voltage low, the error amplifier increases switch current by driving the comp pin high. the error amplifier output clamps internally at a level which sets the peak switch current limit. the tps54341 device provides an accurate current limit threshold with a typical current limit delay of 60 ns. with smaller inductor values, the delay results in a higher peak inductor current. the relationship between the inductor value and the peak inductor current is shown in figure 37 . figure 37. current limit delay to protect the converter in overload conditions at higher switching frequencies and input voltages, the tps54341 device implements a frequency foldback. the oscillator frequency is divided by 1, 2, 4, and 8 as the fb pin voltage falls from 0.8 v to 0 v. the tps54341 device uses a digital frequency foldback to enable synchronization to an external clock during normal startup and fault conditions. during short-circuit events, the inductor current can exceed the peak current-limit because of the high input voltage and the minimum controllable on time. when the output voltage is forced low by the shorted load, the inductor current decreases slowly during the switch off time. the frequency foldback effectively increases the off time by increasing the period of the switching cycle providing more time for the inductor current to ramp down. with a maximum frequency-foldback ratio of 8, there is a maximum frequency at which frequency-foldback protection controls the inductor current. equation 13 calculates the maximum switching frequency at which the inductor current remains under control when v out is forced to v out(sc) . the selected operating frequency should not exceed the calculated value. equation 12 calculates the maximum switching-frequency limitation set by the minimum controllable on time and the input-to-output step-down ratio. setting the switching frequency above this value causes the regulator to skip switching pulses to achieve the low duty cycle required to regulate the output voltage at maximum input voltage. copyright ? 2013, texas instruments incorporated submit documentation feedback 19 product folder links: tps54341 t on t cldelay inductor current (a) clpeak peak inductor current open loop current limit clpeak = v /l x t in cldelay
tps54341 slvsc61 ? november 2013 www.ti.com detailed description (continued) (12) (13) where (for equation 12 and equation 13 ) ? i o = output current ? i cl = current limit ? r dc = inductor resistance ? v in = maximum input voltage ? v out = output voltage ? v out(sc) = output voltage during short ? v d = diode voltage drop ? r ds(on) = switch on resistance ? t on = controllable on time ? ? div , frequency divide equals (1, 2, 4, or 8) synchronization to rt/clk pin the rt/clk pin can receive a frequency synchronization signal from an external system clock. to implement this synchronization feature connect a square wave to the rt/clk pin through either circuit network shown in figure 38 . the square wave applied to the rt/clk pin must switch lower than 0.5 v and higher than 2 v, and must have a pulsewidth greater than 15 ns. the synchronization frequency range is 160 to 2300 khz. the rising edge of the sw synchronizes to the falling edge of rt/clk pin signal. design the external synchronization circuit such that the default-frequency set resistor connects from the rt/clk pin to ground when the synchronization signal is off. when using a low-impedance signal source, the frequency-set resistor connects in parallel with an ac-coupling capacitor to a termination resistor (for example, 50 ) as shown in figure 38 . the two resistors in the series provide the default frequency-setting resistance when the signal source is turned off. the sum of the resistance sets the switching frequency close to the external clk frequency. ac-coupling the synchronization signal the synchronization signal through a 10-pf ceramic capacitor to rt/clk pin is recommended. the first time the rt/clk pulls above the pll threshold the tps54341 device switches from the rt-resistor free-running frequency mode to the pll-synchronized mode. the internal 0.5-v voltage source is removed and the rt/clk pin becomes high impedance as the pll begins to lock onto the external signal. the switching frequency can be higher or lower than the frequency set with the rt/clk resistor. the device transitions from the resistor mode to the pll mode and locks onto the external clock frequency within 78 s. during the transition from the pll mode to the resistor-programmed mode, the switching frequency falls to 150 khz and then increases or decreases to the resistor-programmed frequency when the 0.5-v bias voltage is reapplied to the rt/clk resistor. 20 submit documentation feedback copyright ? 2013, texas instruments incorporated product folder links: tps54341 ( ) ( ) cl dc d out sc div sw(shift) on in cl d ds on i r v v t v i r v ? ? + + ? = ? - + ? ? ? ( ) ( ) o dc out d sw max skip on in o d ds on i r v v 1 t v i r v ? ? + + ? = ? - + ? ?
tps54341 www.ti.com slvsc61 ? november 2013 detailed description (continued) the switching frequency is divided by 8, 4, 2, and 1 as the fb pin voltage ramps from 0 to 0.8 v. the device implements a digital frequency foldback which enables synchronization to an external clock during normal startup and fault conditions. figure 39 , figure 40 and figure 41 show the device synchronized to an external system clock in continuous conduction mode (ccm), discontinuous conduction (dcm), and pulse skip mode (eco-mode). figure 38. synchronizing to a system clock figure 39. plot of synchronizing in ccm figure 40. plot of synchronizing in dcm figure 41. plot of synchronizing in eco-mode copyright ? 2013, texas instruments incorporated submit documentation feedback 21 product folder links: tps54341 rt/clk tps54341 clock source pll rt rt/clk tps54341 hi-z clock source pll rt
tps54341 slvsc61 ? november 2013 www.ti.com detailed description (continued) power good (pwrgd pin) the pwrgd pin is an open-drain output. once the fb pin is between 93% and 106% of the internal voltage reference the pwrgd pin is de-asserted and the pin floats. a pull-up resistor of 1 k to a voltage source that is 5.5 v or less is recommended. a higher pull-up resistance reduces the amount of current drawn from the pull up voltage source when the pwrgd pin is asserted low. a lower pullup resistance reduces the switching noise seen on the pwrgd signal. the pwrgd is in a defined state once the vin input voltage is greater than 2 v but with reduced current sinking capability. the pwrgd will achieve full current sinking capability as vin input voltage approaches 3 v. the pwrgd pin is pulled low when the fb is lower than 90% or greater than 108% of the nominal internal reference voltage. also, the pwrgd is pulled low, if the uvlo or thermal shutdown are asserted or the en pin pulled low. overvoltage protection the tps54341 device incorporates an output overvoltage-protection (ovp) circuit to minimize voltage overshoot when recovering from output fault conditions or strong unload transients in designs with low-output capacitance. for example, when the power-supply output is overloaded the error amplifier compares the actual output voltage to the internal reference voltage. if the fb pin voltage is lower than the internal reference voltage for a considerable time, the output of the error amplifier increases to a maximum voltage corresponding to the peak current-limit threshold. when the overload condition is removed, the regulator output rises and the error amplifier output transitions to the normal operating level. in some applications, the power-supply output voltage increases faster than the response of the error amplifier output resulting in an output overshoot. the ovp feature minimizes output overshoot when using a low-value output capacitor by comparing the fb pin voltage to the rising ovp threshold which is nominally 108% of the internal voltage reference. if the fb pin voltage is greater than the rising ovp threshold, the high-side mosfet disables immediately to minimize output overshoot. when the fb voltage drops below the falling ovp threshold which is nominally 106% of the internal voltage reference, the high-side mosfet resumes normal operation. thermal shutdown the tps54341 device provides an internal thermal shutdown to protect the device when the junction temperature exceeds 176 c. the high-side mosfet stops switching when the junction temperature exceeds the thermal trip threshold. once the die temperature falls below 164 c, the device reinitiates the power-up sequence controlled by discharging the ss/tr pin. small-signal model for loop response figure 42 shows a simplified equivalent model for the tps54341 control loop which is simulated to check the frequency response and dynamic load response. the error amplifier is a transconductance amplifier with a gm ea of 350 a/v. the error amplifier is modeled using an ideal voltage-controlled current source. the resistor r o and capacitor c o model the open-loop gain and frequency response of the amplifier. the 1-mv ac-voltage source between the nodes a and b effectively breaks the control loop for the frequency response measurements. plotting c/a provides the small signal response of the frequency compensation. plotting a/b provides the small signal response of the overall loop. the dynamic loop response is evaluated by replacing r l with a current source with the appropriate load step amplitude and step rate in a time domain analysis. this equivalent model is only valid for ccm operation. 22 submit documentation feedback copyright ? 2013, texas instruments incorporated product folder links: tps54341
tps54341 www.ti.com slvsc61 ? november 2013 detailed description (continued) figure 42. small-signal model for loop response simple small-signal model for peak-current-mode control figure 43 describes a simple small-signal model used to design the frequency compensation. the tps54341 power stage is approximated by a voltage-controlled current source (duty-cycle modulator) supplying current to the output capacitor and load resistor. the control to output transfer function is shown in equation 14 and consists of a dc gain, one dominant pole, and one equivalent-series-resistor (esr) zero. the quotient of the change in switch current and the change in comp pin voltage (node c in figure 42 ) is the power stage transconductance, gm ps . the gm ps for the tps54341 device is 16 a/v. the low-frequency gain of the power stage is the product of the transconductance and the load resistance as shown in equation 15 . as the load current increases and decreases, the low-frequency gain decreases and increases, respectively. this variation with the load seems problematic at first glance, but fortunately the dominant pole moves with the load current (see equation 16 ). the combined effect is highlighted by the dashed line in the right half of figure 43 . as the load current decreases, the gain increases and the pole frequency lowers, keeping the 0-db crossover frequency the same with varying load conditions. the type of output capacitor chosen determines whether the esr zero has a profound effect on the frequency compensation design. using high-esr aluminum-electrolytic capacitors can reduce the number frequency compensation components required to stabilize the overall loop because the phase margin increases by the esr zero of the output capacitor (see functional block diagram ). figure 43. simple small-signal model and frequency response for peak-current-mode control copyright ? 2013, texas instruments incorporated submit documentation feedback 23 product folder links: tps54341 v o r esr c out r l vc gm ps fp fz adc fb comp v o r1 r3 c1 c2 r2 co ro gm ea 350 m a/v 0.8 v power stage gm 12 a/v ps sw r esr c out r l b a c
tps54341 slvsc61 ? november 2013 www.ti.com detailed description (continued) (14) (15) (16) (17) small signal model for frequency compensation the tps54341 device uses a transconductance amplifier for the error amplifier and supports three of the commonly-used frequency compensation circuits. compensation circuits type 2a, type 2b, and type 1 are shown in figure 44 . type 2 circuits are typically implemented in high bandwidth power-supply designs using low- esr output capacitors. the type 1 circuit is used with power-supply designs with high-esr aluminum- electrolytic or tantalum capacitors. equation 18 and equation 19 relate the frequency response of the amplifier to the small signal model in figure 44 . the open-loop gain and bandwidth are modeled using the r o and c o shown in figure 44 . see the application information section for a design example using a type 2a network with a low-esr output capacitor. equation 18 through equation 27 are provided as a reference. an alternative is to use webench software tools to create a design based on the power-supply requirements (go to www.ti.com/webench for more information). figure 44. types of frequency compensation 24 submit documentation feedback copyright ? 2013, texas instruments incorporated product folder links: tps54341 v ref v o r1 r3 c1 c2 r2 c o r o gm ea comp fb type 2a type 2b type 1 c2 r3 c1 z out esr 1 ? c r 2 = p p out l 1 ? c r 2 = p ps l adc = gm r z out p s 1 2 ? v adc vc s 1 2 ? ? ? + ? p ? = ? ? + ? p ?
tps54341 www.ti.com slvsc61 ? november 2013 detailed description (continued) figure 45. frequency response of the type 2a and type 2b frequency compensation (18) (19) (20) (21) (22) (23) (24) (25) (26) (27) copyright ? 2013, texas instruments incorporated submit documentation feedback 25 product folder links: tps54341 ( ) o o 1 p2 type 1 2 r c2 c = p + o o 1 p2 type 2b 2 r3 r c = p p ( ) o o 1 p2 type 2a 2 r3 r c2 c = p + p 1 z1 2 r3 c1 = p 1 p1 2 ro c1 = p ea o r2 a1 gm r r3 r1 r2 = + p ea o r2 a0 gm r r1 r2 = + z1 p1 p2 s 1 2 ? ea a0 s s 1 1 2 ? 2 ? ? ? + ? p ? = ? ? ? ? + + ? ? p p ? ? p ea o gm c = 2 bw (hz) ( ) o ea aol v / v r gm = a0a1 p1 z1 p2 aol bw
tps54341 slvsc61 ? november 2013 www.ti.com application information design guide ? step-by-step design procedure this guide illustrates the design of a high frequency switching regulator using ceramic output capacitors. a few parameters must be known in order to start the design process. these requirements are typically determined at the system level. the necessary calculations can be done using webench or the excel spreadsheet ( slvc452 ) located on the product. this design starts from the following known parameters. output voltage 3.3 v transient response 0.875 a to 2.625 a load step v out = 4 % maximum output current 3.5 a input voltage 12 v nominal 6 v to 42 v output voltage ripple 0.5% of v out start input voltage (rising vin) 5.75 v stop input voltage (falling vin) 4.5 v selecting the switching frequency the first step is to choose a switching frequency for the regulator. typically, the designer uses the highest switching frequency possible because this produces the smallest solution size. high switching frequency allows for lower value inductors and smaller output capacitors compared to a power supply that switches at a lower frequency. the switching frequency that can be selected is limited by the minimum on-time of the internal power switch, the input voltage, the output voltage and the frequency-foldback protection. equation 12 and equation 13 must be used to calculate the upper limit of the switching frequency for the regulator. choose the lower value result from the two equations. switching frequencies higher than these values results in pulse skipping or the lack of overcurrent protection during a short circuit. the typical minimum on time, t onmin , is 135 ns for the tps54341 device. for this example, the output voltage is 3.3 v and the maximum input voltage is 42 v, which allows for a maximum switch frequency up to 712 khz to avoid pulse skipping from equation 12 . to ensure overcurrent runaway is not a concern during short circuits use equation 13 to determine the maximum switching frequency for frequency foldback protection. with a maximum input voltage of 42 v, assuming a diode voltage of 0.7 v, inductor resistance of 21 m , switch resistance of 87 m , a current-limit value of 4.7 a and short circuit output voltage of 0.1 v, the maximum switching frequency is 1260 khz. for this design, a lower switching frequency of 600 khz is chosen to operate comfortably below the calculated maximums. to determine the timing resistance for a given switching frequency, use equation 10 or the curve in figure 6 . the switching frequency is set by resistor r 3 shown in figure 46 . for 600 khz operation, the closest standard value resistor is 162 k . (28) (29) (30) 26 submit documentation feedback copyright ? 2013, texas instruments incorporated product folder links: tps54341 w w 0.991 92417 rt (k ) = = 163 k 600 (khz) sw(shift) 8 4.7 a x 21 m 0.1 v 0.7 v 1260 khz 135 ns 42 v - 4.7 a x 87 m 0.7 v w + + ? ? = = ? w + ? f sw(max skip) 1 3.5 a x 21 m 3.3 v 0.7 v 712 khz 135ns 42 v - 3.5 a x 87 m 0.7 v ? ? w + + = = ? w + ? f
tps54341 www.ti.com slvsc61 ? november 2013 figure 46. 3.3-v output tps54341 design example output inductor selection (l o ) to calculate the minimum value of the output inductor, use equation 31 . k ind is a ratio that represents the amount of inductor ripple current relative to the maximum output current. the inductor ripple current is filtered by the output capacitor. therefore, choosing high inductor ripple currents impacts the selection of the output capacitor because the output capacitor must have a ripple current rating equal to or greater than the inductor ripple current. in general, the inductor ripple value is at the discretion of the designer, however, the following guidelines may be used. for designs using low esr output capacitors such as ceramics, a value as high as k ind = 0.3 may be desirable. when using higher esr output capacitors, k ind = 0.2 yields better results. because the inductor ripple current is part of the current mode pwm control system, the inductor ripple current should always be greater than 150 ma for stable pwm operation. in a wide input voltage regulator, it is best to choose relatively large inductor ripple current. this provides sufficienct ripple current with the input voltage at the minimum. for this design example, k ind = 0.3 and the minimum inductor value is calculated to be 4.8 h. the nearest standard value is 5.6 h. it is important that the rms current and saturation current ratings of the inductor not be exceeded. the rms and peak inductor current can be found from equation 33 and equation 34 . for this design, the rms inductor current is 3.5 a and the peak inductor current is 3.95 a. the chosen inductor is a we 7443552560, which has a saturation current rating of 7.5 a and an rms current rating of 6.7 a. as the equation set demonstrates, lower ripple currents will reduce the output voltage ripple of the regulator but will require a larger value of inductance. selecting higher ripple currents will increase the output voltage ripple of the regulator but allow for a lower inductance value. the current flowing through the inductor is the inductor ripple current plus the output current. during power up, faults or transient load conditions, the inductor current can increase above the peak inductor current level calculated above. in transient conditions, the inductor current can increase up to the switch current limit of the device. for this reason, the most conservative design approach is to choose an inductor with a saturation current rating equal to or greater than the switch current limit of the tps54341 device which is nominally 5.5 a. copyright ? 2013, texas instruments incorporated submit documentation feedback 27 product folder links: tps54341 vin gnd en gnd 6 v to 42 v 2.2f c1 2.2f c2 2.2f c3 dnp gnd gnd gnd 88.7k r2 365k r1 gnd tp1 tp2 1 2 j3 1 2 j4 gnd 2.2f c10 dnp 1 2 j2 2 1 + c11 dnp 0.01f c13 pwrgd tp10 fb boot 1 vin 2 en 3 ss/tr 4 rt/clk 5 fb 6 comp 7 gnd 8 sw 9 pwrgd 10 pad u1 tps54341dpr 162k r3 11.5k r4 47pf c8 5600pf c5 1 2 j5 ss/tr gnd gnd ss/tr gnd ss/tr 0.1f c4 3.3v 3.5a vout gnd 47f c9 dnp 47f c7 dnp 100f c6 gnd gnd 49.9 r7 31.6k r5 10.2k r6 tp6 tp8 tp4 tp7 tp5 tp3 5.6h l1 7443552560 1 2 j1 2 1 + c12 dnp 1 3 2 d1 pds560-13 fb pwrgd pull up tp9 1.00k r8
tps54341 slvsc61 ? november 2013 www.ti.com (31) spacer (32) spacer (33) spacer (34) output capacitor there are three primary considerations for selecting the value of the output capacitor. the output capacitor determines the modulator pole, the output voltage ripple, and how the regulator responds to a large change in load current. the output capacitance needs to be selected based on the most stringent of these three criteria. the desired response to a large change in the load current is the first criteria. the output capacitor needs to supply the increased load current until the regulator responds to the load step. the regulator does not respond immediately to a large, fast increase in the load current such as transitioning from no load to a full load. the regulator usually needs two or more clock cycles for the control loop to sense the change in output voltage and adjust the peak switch current in response to the higher load. the output capacitance must be large enough to supply the difference in current for two clock cycles to maintain the output voltage within the specified range. equation 35 shows the minimum output capacitance necessary, where i out is the change in output current, ? sw is the regulators switching frequency and v out is the allowable change in the output voltage. for this example, the transient load response is specified as a 4% change in v out for a load step from 0.875 a to 2.625 a. therefore, i out is 2.625 a ? 0.875 a = 1.75 a and v out = 0.04 3.3 = 0.13 v. using these numbers gives a minimum capacitance of 44.9 f. this value does not take the esr of the output capacitor into account in the output voltage change. for ceramic capacitors, the esr is usually small enough to be ignored. aluminum electrolytic and tantalum capacitors have higher esr that must be included in load step calculations. the output capacitor must also be sized to absorb energy stored in the inductor when transitioning from a high to low load current. the catch diode of the regulator can not sink current so energy stored in the inductor can produce an output voltage overshoot when the load current rapidly decreases. a typical load step response is shown in figure 47 . the excess energy absorbed in the output capacitor will increase the voltage on the capacitor. the capacitor must be sized to maintain the desired output voltage during these transient periods. equation 36 calculates the minimum capacitance required to keep the output voltage overshoot to a desired value, where l o is the value of the inductor, i oh is the output current under heavy load, i ol is the output under light load, v f is the peak output voltage, and v i is the initial voltage. for this example, the worst case load step will be from 2.625 a to 0.875 a. the output voltage increases during this load transition and the stated maximum in our specification is 4 % of the output voltage. this makes v f = 1.04 3.3 = 3.432. v i is the initial capacitor voltage which is the nominal output voltage of 3.3 v. using these numbers in equation 36 yields a minimum capacitance of 38.6 f. equation 37 calculates the minimum output capacitance needed to meet the output voltage ripple specification, where ? sw is the switching frequency, v oripple is the maximum allowable output voltage ripple, and i ripple is the inductor ripple current. equation 37 yields 11.4 f. equation 38 calculates the maximum esr an output capacitor can have to meet the output voltage ripple specification. equation 38 indicates the esr should be less than 18 m . the most stringent criteria for the output capacitor is 44.9 f required to maintain the output voltage within regulation tolerance during a load transient. 28 submit documentation feedback copyright ? 2013, texas instruments incorporated product folder links: tps54341 ( ) = + = + = ripple out l peak i 0.905 a i i 3.5 a 3.95 a 2 2 ( ) ( ) ( ) ( ) ( ) ( ) ( ) 2 2 out out in max 2 2 out l rms o sw in max v v v 3.3 v 42 v C 3.3 v 1 1 i i 3.5 a 3.5 a 12 v l 12 42 v 5.6 h 600 khz ? ? - ? ? ? = + = + = ? ? ? ? ? ? ? ( ) ( ) out out in max ripple o sw in max v (v v ) 3.3 v (42 v 3.3 v) i 0.905 a v l ? 42 v 5.6 h 600 khz - = = = C ( ) ( ) ( ) out in max out o min out ind sw in max v v v 42 v 3.3 v 3.3 v l 4.8 h i k v 3.5 a 0.3 42 v 600 khz - = = = C ?
tps54341 www.ti.com slvsc61 ? november 2013 capacitance de-ratings for aging, temperature and dc bias increases this minimum value. for this example, a 100- f ceramic capacitor with 5 m of esr is used. the derated capacitance is 70 f, well above the minimum required capacitance of 44.9 f. capacitors are generally rated for a maximum ripple current that can be filtered without degrading capacitor reliability. some capacitor data sheets specify the root mean square (rms) value of the maximum ripple current. equation 39 can be used to calculate the rms ripple current that the output capacitor must support. for this example, equation 39 yields 261 ma. (35) (36) (37) (38) (39) catch diode the tps54341 device requires an external catch diode between the sw pin and gnd. the selected diode must have a reverse voltage rating equal to or greater than v in(max) . the peak current rating of the diode must be greater than the maximum inductor current. schottky diodes are typically a good choice for the catch diode due to their low forward voltage. the lower the forward voltage of the diode, the higher the efficiency of the regulator. typically, diodes with higher voltage and current ratings have higher forward voltages. a diode with a minimum of 42 v reverse voltage is preferred to allow input voltage transients up to the rated voltage of the tps54341 device. for the example design, the pds560 schottky diode is selected for its lower forward voltage and good thermal characteristics compared to smaller devices. the typical forward voltage of the pds560 is 0.55 v at 3.5 a. the diode must also be selected with an appropriate power rating. the diode conducts the output current during the off-time of the internal power switch. the off-time of the internal switch is a function of the maximum input voltage, the output voltage, and the switching frequency. the output current during the off-time is multiplied by the forward voltage of the diode to calculate the instantaneous conduction losses of the diode. at higher switching frequencies, the ac losses of the diode must be taken into account. the ac losses of the diode are due to the charging and discharging of the junction capacitance and reverse recovery charge. equation 40 is used to calculate the total power dissipation, including conduction losses and ac losses of the diode. the pds560 diode has a junction capacitance of 90 pf at 42 v input voltage. using equation 40 , the total loss in the diode is 2.27 w. if the power supply spends a significant amount of time at light load currents or in sleep mode, consider using a diode which has a low leakage current and slightly higher forward voltage drop. (40) copyright ? 2013, texas instruments incorporated submit documentation feedback 29 product folder links: tps54341 ( ) ( ) ( ) ( ) ( ) 2 out out in max j sw in d in max 2 v v i v d c v v d p v 2 42 v - 3.3 v 3.5 a x 0.55 v 90 pf x 600 khz x (42 v 0.55 v) 2.27 w 42 v 2 - + = + = + + = f f f ( ) ( ) ( ) ( ) f - = = = m out out in max cout(rms) o sw in max v v v 3.3 v 42 v - 3.3 v i 261 ma 12 v l 12 42 v 5.6 h 600 khz < = = w oripple esr ripple v 16.5 mv r 18 m i 0.905 a f > = = m ? ? ? ? ? ? ? ? out sw oripple ripple 1 1 1 1 c x 11.4 f 16.5 mv 8 8 x 600 khz v 0.905 a i ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) > = m = m - 2 2 2 2 oh ol out o 2 2 2 2 f i i - i 2.625 a - 0.875 a c l x 5.6 h x 38.6 f 3.432 v 3.3 v v - v f d > = = m d out out sw out 2 i 2 1.75 a c 44.9 f v 600 khz x 0.13 v
tps54341 slvsc61 ? november 2013 www.ti.com input capacitor the tps54341 device requires a high-quality ceramic-type x5r or x7r input-decoupling capacitor with at least 3 f of effective capacitance. some applications will benefit from additional bulk capacitance. the effective capacitance includes any loss of capacitance due to dc bias effects. the voltage rating of the input capacitor must be greater than the maximum input voltage. the capacitor must also have a ripple current rating greater than the maximum input current ripple of the tps54341 device. the input ripple current can be calculated using equation 41 . the value of a ceramic capacitor varies significantly with temperature and the dc bias applied to the capacitor. the capacitance variations due to temperature can be minimized by selecting a dielectric material that is more stable over temperature. x5r and x7r ceramic dielectrics are usually selected for switching regulator capacitors because they have a high capacitance to volume ratio and are fairly stable over temperature. the input capacitor must also be selected with consideration for the dc bias. the effective value of a capacitor decreases as the dc bias across a capacitor increases. for this example design, a ceramic capacitor with at least a 42 v voltage rating is required to support the maximum input voltage. common standard ceramic capacitor voltage ratings include 4 v, 6.3 v, 10 v, 16 v, 25 v, 50 v, or 100 v. for this example, two 2.2- f 100-v capacitors in parallel are used. table 1 shows several choices of high voltage capacitors. the input capacitance value determines the input ripple voltage of the regulator. the input voltage ripple can be calculated using equation 42 . using the design example values, i out = 3.5 a, c in = 4.4 f, ? sw = 600 khz, yields an input voltage ripple of 331 mv and a rms input ripple current of 1.74 a. (41) (42) table 1. capacitor types vendor value ( f) eia size voltage (v) dialectric comments 1 to 2.2 100 1210 grm32 series 1 to 4.7 50 murata 1 100 1206 grm31 series 1 to 2.2 50 1 to 1.8 50 2220 1 to 1.2 100 vishay vj x7r series 1 to 3.9 50 2225 1 to 1.8 100 x7r 1 to 2.2 100 1812 c series c4532 1.5 to 6.8 50 tdk 1 to 2.2 100 1210 c series c3225 1 to 3.3 50 1 to 4.7 50 1210 1 100 avx x7r dielectric series 1 to 4.7 50 1812 1 to 2.2 100 30 submit documentation feedback copyright ? 2013, texas instruments incorporated product folder links: tps54341 f d = = = m out in in sw i 0.25 3.5 a 0.25 v 331 mv c 4.4 f 600 khz ( ) ( ) ( ) ( ) ( ) ( ) - = = = out in min out out ci rms in min in min v v 6 v - 3.3 v v 3.3 v i i x x 3.5 a 1.74 a v v 6 v 6 v
tps54341 www.ti.com slvsc61 ? november 2013 slow-start capacitor the slow-start capacitor determines the minimum amount of time it will take for the output voltage to reach its nominal programmed value during power up. this is useful if a load requires a controlled voltage slew rate. this is also used if the output capacitance is large and would require large amounts of current to quickly charge the capacitor to the output voltage level. the large currents necessary to charge the capacitor may make the tps54341 device reach the current limit or excessive current draw from the input power supply may cause the input voltage rail to sag. limiting the output voltage slew rate solves both of these problems. the slow-start time must be long enough to allow the regulator to charge the output capacitor up to the output voltage without drawing excessive current. equation 43 can be used to find the minimum slow-start time, t ss , necessary to charge the output capacitor, c out , from 10% to 90% of the output voltage, v out , with an average slow-start current of i ssavg . in the example, to charge the effective output capacitance of 70 f up to 3.3 v with an average current of 1 a requires a 0.2-ms slow-start time. once the slow-start time is known, the slow-start capacitor value can be calculated using equation 5 . for the example circuit, the slow-start time is not too critical because the output capacitor value is 100 f which does not require much current to charge to 3.3 v. the example circuit has the slow-start time set to an arbitrary value of 3.5 ms which requires a 9.3-nf slow-start capacitor calculated by equation 44 . for this design, the next larger standard value of 10 nf is used. (43) (44) bootstrap capacitor selection a 0.1- f ceramic capacitor must be connected between the boot and sw pins for proper operation. a ceramic capacitor with x5r or better grade dielectric is recommended. the capacitor must have a 10 v or higher voltage rating. undervoltage lockout set point the undervoltage lockout (uvlo) can be adjusted using an external voltage divider on the en pin of the tps54341 device. the uvlo has two thresholds, one for power up when the input voltage is rising and one for power down or brown outs when the input voltage is falling. for the example design, the supply should turn on and start switching once the input voltage increases above 5.75 v (uvlo start). after the regulator starts switching, it should continue to do so until the input voltage falls below 4.5 v (uvlo stop). programmable uvlo threshold voltages are set using the resistor divider of r uvlo1 and r uvlo2 between vin and ground connected to the en pin. equation 3 and equation 4 calculate the resistance values necessary. for the example application, a 365 k between vin and en (r uvlo1 ) and a 88.7 k between en and ground (r uvlo2 ) are required to produce the 8-v and 6.25-v start and stop voltages. (45) (46) copyright ? 2013, texas instruments incorporated submit documentation feedback 31 product folder links: tps54341 ss ss ss ref t (ms) i (a) 1.7 a c (nf) = 3.5 ms 9.3 nf v (v) 0.8 (0.8 v 0.8 ) = = out out ss ssavg c v 0.8 t i > = = = w + m + w ena uvlo2 start ena 1 uvlo1 v 1.2 v r 87.8 k v - v 5.75 v - 1.2 v 1.2 a i 365 k r = = = w m start stop uvlo1 hys v - v 5.75 v - 4.5 v r 368 k i 3.4 a
tps54341 slvsc61 ? november 2013 www.ti.com output voltage and feedback resistors selection the voltage divider of r5 and r6 sets the output voltage. for the example design, 10.2 k was selected for r6. using equation 2 , r5 is calculated as 31.9 k . the nearest standard 1% resistor is 31.6 k . due to the input current of the fb pin, the current flowing through the feedback network should be greater than 1 a to maintain the output voltage accuracy. this requirement is satisfied if the value of r6 is less than 800 k . choosing higher resistor values decreases quiescent current and improves efficiency at low output currents but may also introduce noise immunity problems. (47) compensation there are several methods to design compensation for dc-dc regulators. the method presented here is easy to calculate and ignores the effects of the slope compensation that is internal to the device. because the slope compensation is ignored, the actual crossover frequency will be lower than the crossover frequency used in the calculations. this method assumes the crossover frequency is between the modulator pole and the esr zero and the esr zero is at least ten-times greater the modulator pole. to get started, the modulator pole, ? p(mod) , and the esr zero, ? z1 must be calculated using equation 48 and equation 49 . for c out , use a derated value of 70 f. use equations equation 50 and equation 51 to estimate a starting point for the crossover frequency, ? co . for the example design, ? p(mod) is 2411 hz and ? z(mod) is 455 khz. equation 49 is the geometric mean of the modulator pole and the esr zero and equation 51 is the mean of modulator pole and the switching frequency. equation 50 yields 33.1 khz and equation 51 gives 26.9 khz. use the lower value of equation 50 or equation 51 for an initial crossover frequency. for this example, the target ? co is 26.9 khz. next, the compensation components are calculated. a resistor in series with a capacitor is used to create a compensating zero. a capacitor in parallel to these two components forms the compensating pole. (48) (49) (50) (51) to determine the compensation resistor, r4, use equation 52 . assume the power stage transconductance, gmps, is 12 a/v. the output voltage, v o , reference voltage, v ref , and amplifier transconductance, gmea, are 5 v, 0.8 v and 350 a/v, respectively. r4 is calculated to be 11.6 k and a standard value of 11.5 k is selected. use equation 53 to set the compensation zero to the modulator pole frequency. equation 53 yields 5740 pf for compensating capacitor c5. 5600 pf is used for this design. (52) (53) 32 submit documentation feedback copyright ? 2013, texas instruments incorporated product folder links: tps54341 f = = = p p w p(mod) 1 1 c5 5740 pf 2 r4 x 2 11.5 k x 2411 hz co out out ps ref ea 2 c v 2 26.9 khz 70 f 3.3 v r4 11.6 k gm v x gm 12 a / v 0.8 v 350 a / v ? ? ? ? p ? ? p ? ? ? = = = w ? ? ? ? ? ? ? ? ? f f f = = = sw co p(mod) x 600 khz 2411 hz x 26.9 khz 2 2 f f f = = = co p(mod) x z(mod) 2411 hz x 455 khz 33.1 khz ( ) f = = = p p w m z mod esr out 1 1 455 khz 2 r c 2 5 m 70 f ( ) ( ) f = = = p p m out max p mod out out i 3.5 a 2411 hz 2 v c 2 3.3 v 70 f ? ? = = w = w ? ? out hs ls v - 0.8 v 3.3 v - 0.8 v r r x 10.2 k x 31.9 k 0.8 v 0.8 v
tps54341 www.ti.com slvsc61 ? november 2013 a compensation pole can be implemented if desired by adding capacitor c8 in parallel with the series combination of r4 and c5. use the larger value calculated from equation 54 and equation 55 for c8 to set the compensation pole. the selected value of c8 is 47 pf for this design example. (54) (55) discontinuous conduction mode and eco-mode boundary with an input voltage of 12 v, the power supply enters discontinuous conduction mode when the output current is less than 340 ma. the power supply enters eco-mode when the output current is lower than 30 ma. the input current draw is 260 a with no load. copyright ? 2013, texas instruments incorporated submit documentation feedback 33 product folder links: tps54341 sw 1 1 c8 46.1 pf r4 11.5 k 600 khz = = = p w p ? m w = = = w out esr c x r 70 f x 5 m c8 30.4 pf r4 11.5 k
tps54341 slvsc61 ? november 2013 www.ti.com application curves figure 47. load transient figure 48. line transient (8 v to 40 v) figure 49. startup with vin figure 50. startup with en figure 51. output ripple ccm figure 52. output ripple dcm 34 submit documentation feedback copyright ? 2013, texas instruments incorporated product folder links: tps54341 time = 2 s/div m 1 a/div 10 v/div 20 mv/div c2: v ac coupled out c1: sw c4: i l i = 3.5 a out c2c4 c1 time = 2 s/div m 500 ma/div 10 v/div 10 mv/div c2: v ac coupled out c1: sw c4: i l i = 100 ma out c2 c4 c1 time = 2 ms/div 2 v/div 5 v/div 2 v/div c3: en c2: v out c3c2 c1 c1: v in time = 100 s/div m 100 mv/div c3: v ac coupled out 1 a/div c4: i out c4c3 time = 4 ms/div 20 mv/div 10 v/div v v offset out -3.3 v in
tps54341 www.ti.com slvsc61 ? november 2013 figure 53. output ripple psm figure 54. input ripple ccm figure 55. input ripple dcm figure 56. low dropout operation figure 57. low dropout operation figure 58. low dropout operation copyright ? 2013, texas instruments incorporated submit documentation feedback 35 product folder links: tps54341 time = 40 s/div m 2 v/div v in i = 100 ma en floating out v out time = 40 s/div m 2 v/div v in i = 1 a en floating out v out time = 2 s/div m 500 ma/div 10 v/div 50 mv/div c3: v ac coupled in c1: sw c4: i l i = 100 ma out c3 c4 c1 time = 20 s/div m 200 ma/div 2 v/div 20 mv/div c3: v ac coupled out c1: sw c4: i l no loaden floating c3 c4 v = 5.5 v v = 5 v in out time = 2 s/div m 1 a/div 10 v/div 200 mv/div c3: v ac coupled in c1: sw c4: i l i = 3.5 a out c2c4 c1 time = 2 ms/div 200 ma/div 10 v/div 20 mv/div no load c1: sw c4: i l c2: v ac coupled out c2 c4 c1
tps54341 slvsc61 ? november 2013 www.ti.com figure 59. efficiency versus load current figure 60. light load efficiency figure 61. efficiency versus load current figure 62. light load efficiency figure 63. overall loop frequency response figure 64. regulation versus load current 36 submit documentation feedback copyright ? 2013, texas instruments incorporated product folder links: tps54341 0.10 0.08 0.06 0.04 0.02 0.00 0.02 0.04 0.06 0.08 0.10 0 1 2 3 4 output volttage deviation (%) output current (a) c006 v in = 12 v v out = 3.3 v f sw = 600 khz 10 100 1k 10k 100k 180 120 60 0 60 120 180 60 40 20 0 20 40 60 phase (deg) gain (db) frequency (hz) gain (db) phase (deg) c005 v in = 12 v v out = 3.3 v i out = 3.5 a f sw = 600 khz 60 65 70 75 80 85 90 95 100 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 efficiency (%) output current (a) vin = 7v vin = 12v vin = 24v vin = 36v c003 v in = 7 v v in = 12 v v in = 24 v v in = 36 v v out 9| sw = 600 khz 0 10 20 30 40 50 60 70 80 90 100 0.001 0.01 0.1 1 efficiency (%) output current (a) vin = 7v vin = 12v vin = 24v vin = 36v c004 v in = 7 v v in = 12 v v in = 24 v v in = 36 v v out 9| sw = 600 khz 0 10 20 30 40 50 60 70 80 90 100 0.001 0.01 0.1 1 efficiency (%) output current (a) vin = 6v vin = 12v vin = 24v vin = 36v c002 v in = 6 v v in = 12 v v in = 24 v v in = 36 v v out 9| sw = 600 khz 60 65 70 75 80 85 90 95 100 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 efficiency (%) output current (a) vin = 6v vin = 12v vin = 24v vin = 36v c001 v in = 6 v v in = 12 v v in = 24 v v in = 36 v v out a ?x? s u ? sw = 600 khz
tps54341 www.ti.com slvsc61 ? november 2013 figure 65. regulation versus input voltage copyright ? 2013, texas instruments incorporated submit documentation feedback 37 product folder links: tps54341 0.10 0.08 0.06 0.04 0.02 0.00 0.02 0.04 0.06 0.08 0.10 0 5 10 15 20 25 30 35 40 45 output voltage deviation (%) input voltage (v) c007 i out = 1.75 v v out = 3.3 v f sw = 600 khz
tps54341 slvsc61 ? november 2013 www.ti.com power dissipation estimate the following formulas show how to estimate the tps54341 power dissipation under continuous conduction mode (ccm) operation. these equations should not be used if the device is operating in discontinuous conduction mode (dcm). the power dissipation of the ic includes conduction loss (p cond ), switching loss (p sw ), gate drive loss (p gd ) and supply current (p q ). example calculations are shown with the 12 v typical input voltage of the design example. (56) spacer (57) spacer (58) spacer (59) where: i out is the output current (a). r ds(on) is the on-resistance of the high-side mosfet ( ). v out is the output voltage (v). v in is the input voltage (v). ? sw is the switching frequency (hz). t rise is the sw pin voltage rise time and can be estimated by trise = v in 0.16 ns/v + 3 ns q g is the total gate charge of the internal mosfet i q is the operating nonswitching supply current therefore, (60) for given t a , (61) for given t j(max) = 150 c (62) where: p tot is the total device power dissipation (w). t a is the ambient temperature ( c). t j is the junction temperature ( c). r th is the thermal resistance ( c/w). t j(max) is maximum junction temperature ( c). t a(max) is maximum ambient temperature ( c). there will be additional power losses in the regulator circuit due to the inductor ac and dc losses, the catch diode and pcb trace resistance impacting the overall efficiency of the regulator. 38 submit documentation feedback copyright ? 2013, texas instruments incorporated product folder links: tps54341 ( ) ( ) = - th tot a max j max t t r p = + j a th tot t t r p = + + + = + + + = tot cond sw gd q p p p p p 0.31 w 0.123 w 0.022 w 0.0018 w 0.457 w = = m = q in q p v i 12 v 146 a 0.0018 w f = = = gd in g sw p v q 12 v 3nc 600 khz 0.022 w f = = = sw in sw out rise p v i t 12 v 600 khz 3.5 a 4.9 ns 0.123 w ( ) ( ) 2 2 out cond out ds on in v 3.3 v p i r 3.5 a 87 m 0.31 w v 12 v ? ? = = w = ? ?
tps54341 www.ti.com slvsc61 ? november 2013 layout layout is a critical portion of good power supply design. there are several signal paths that conduct fast changing currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise or degrade performance. to reduce parasitic effects, the vin pin should be bypassed to ground with a low esr ceramic bypass capacitor with x5r or x7r dielectric. care should be taken to minimize the loop area formed by the bypass capacitor connections, the vin pin, and the anode of the catch diode. see figure 66 for a pcb layout example. the gnd pin should be tied directly to the power pad under the ic and the power pad. the power pad should be connected to internal pcb ground planes using multiple vias directly under the ic. the sw pin should be routed to the cathode of the catch diode and to the output inductor. because the sw connection is the switching node, the catch diode and output inductor should be located close to the sw pins, and the area of the pcb conductor minimized to prevent excessive capacitive coupling. for operation at full rated load, the top side ground area must provide adequate heat dissipating area. the rt/clk pin is sensitive to noise so the rt resistor should be located as close as possible to the ic and routed with minimal lengths of trace. the additional external components can be placed approximately as shown. it may be possible to obtain acceptable performance with alternate pcb layouts, however this layout has been shown to produce good results and is meant as a guideline. figure 66. pcb layout example estimated circuit area boxing in the components in the design of figure 46 the estimated printed circuit board area is 1.025 in 2 (661 mm 2 ). this area does not include test points or connectors. copyright ? 2013, texas instruments incorporated submit documentation feedback 39 product folder links: tps54341 bootvin en rt/ clk sw gnd comp fb inputbypass capacitor uvloadjust resistors frequencyset resistor compensationnetwork resistordivider outputinductor output capacitor v out v in topside ground area catchdiode route boot capacitor trace on another layer to provide wide path for topside ground thermal via signal via ss/tr pwrgd soft-start capacitor
tps54341 slvsc61 ? november 2013 www.ti.com figure 67. tps54341 inverting power supply based on the application note, slva317 figure 68. tps54341 split rail power supply based on the application note, slva369 40 submit documentation feedback copyright ? 2013, texas instruments incorporated product folder links: tps54341 sw vin gnd boot fb comp tps54341 en rt/clk cpole czero rcomp rt coneg lo cboot cin r1 r2 cd vin voneg + + gnd vopos copos + c ss ss/tr sw vin gnd boot fb comp tps54341 en rt/clk cpole czero rcomp rt co lo cboot cin r1 r2 cd vin vout + + gnd c ss ss/tr
package option addendum www.ti.com 17-may-2014 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples TPS54341DPRR active wson dpr 10 3000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -40 to 85 tps 54341 tps54341dprt active wson dpr 10 250 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -40 to 85 tps 54341 (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device. (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release.
package option addendum www.ti.com 17-may-2014 addendum-page 2 in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis.
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant TPS54341DPRR wson dpr 10 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 q2 tps54341dprt wson dpr 10 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 q2 package materials information www.ti.com 18-dec-2013 pack materials-page 1
*all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) TPS54341DPRR wson dpr 10 3000 367.0 367.0 35.0 tps54341dprt wson dpr 10 250 210.0 185.0 35.0 package materials information www.ti.com 18-dec-2013 pack materials-page 2

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